An Improved Quad Itoh-Tsujii Algorithm for FPGAs
Keywords:
Field-programmable gate-array (FPGA)-based designs,
Quad Itoh-Tsujii Algorithm (QITA),
Lookup Table (LUT)
Article ID: 10.20130612
Details
Article ID: 10.20130612
In this paper, we propose an improved quad Itoh-Tsujii algorithm to compute multiplicative inverse efficiently on Field-programmable gate-arrays (FPGA) platforms for binary fields generated by irreducible trinomials. Efficiency is obtained by eliminating the precomputation steps required in conventional quad-ITA (QITA) scheme. Experimental results show that the proposed architecture improves the performance on FPGAs compared to existing techniques.
