抄録
A MASH 1-1-1 ΔΣ time-to-digital converter (TDC), based on two-stage time quantization, was designed with a 0.13 μm CMOS process and a 1.2 V supply. A classical delay line and a Vernier delay line were used for coarse and fine quantization, respectively. Third-order noise-shaping was achieved using the proposed MASH 1-1-1 ΔΣ modulator. Simulation results showed that a resolution of up to 5.5 ps and a measurement range of 38.4 ns could be achieved. The proposed TDC consumes 4.9 mW and occupies 0.28 mm2.
