On-chip long-term jitter measurement for PLL based on undersampling technique

Abstract

An all-digital circuit for on-chip measuring the long-term jitter of Phase-Locked Loop (PLL) using the undersampling technique is presented in this paper. The circuit comprises the undersampling circuit, which samples the PLL output signal and the data analysis circuit, which calculates the statistical value of the jitter. The data statistics approach is based on accumulating data from multiple edge regions with cycle edge alignment, which is suitable for measuring the long-term jitter of PLL clock signal. The proposed built-in self-test (BIST) circuit can test the PLL output signal whose frequency is greater than 1GHz. And it can provide high measurement resolution that is up to 1 ps. The circuit was designed in Verilog, and fabricated in TSMC 130 nm CMOS process. Simulated results show the possibility of detecting 45 ps RMS long-term jitter of a 1GHz clock with less than 2% error.