IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Design of a Bitmap-based QoS-aware Memory Controller for a Packet Memory
Seunghak YuSungroh YoonEui-Young ChungHyuk-Jun Lee
Author information
JOURNAL FREE ACCESS Advance online publication

Article ID: 11.20130983


A packet memory controller in routers accesses the packet memory according to the QoS requirements of packets. The previous QoS-aware controller using a feedback control loop degenerates into round robin scheduling under temporary overload and suffers from slow response. We propose a new packet memory controller that estimates input load accurately and rapidly and schedules different classes using a flexible bitmap scheduler. The results show that under temporary overload or rapidly changing input loads, it can successfully meet the latency requirements by showing only less than 2 % difference from the requirement of the high priority class.

Information related to the author
© 2014 by The Institute of Electronics, Information and Communication Engineers