抄録
Scaling the feature size under 0.1 micron leads to the domination of leakage power along with the consumption by interconnects also. Among alternatives for power optimization, the circuit level approach is the best option for low power consumption which is used in this work to incorporate a novel MOS Switch Integrated Ultra-Low Power (MOSSI-ULP) 1-bit full adder using 32nm BPTM file. It is then used as a base cell in an array multiplier. Its performance is compared with similar kind of adders like SERF, ULPFA, TGA, TFA and BBL-PT. The analysis shows that the proposed design consumes a maximum of 11 time lower average power than ULPFA. Though MOSSI-ULP switches with a moderate frequency, it requires 17 times less PDP than ULPFA and maximum of 3 times less area.
