抄録
A digital intensive Clock Recovery Circuit applied to HF-Band active RFID tag is proposed in this paper. Based on the signal interface of ISO/IEC 14443 Type-A protocol, in order to achieve the coherent demodulation in receiving mode, a modified digital intensive PLL is utilized to accurately extract the carrier’s frequency and phase information from the received ASK 100% modulation signal. Meanwhile, in transmitting mode, the proposed PLL can also effectively calibrate the system clock’s frequency error and phase deviation in a discontinuous mode. The whole chip of Clock Recovery Circuit was implemented in 180 nm EEPROM technology. The measurement results show that the maximum power consumption of Clock Recovery Circuit is about 900μW at 1.8V power supply, and the phase deviation in the demodulation and modulation period is respectively less than 10º and 20º.
