Optimization of CMOS power-cell layout for improving junction breakdown

Ockgoo Lee; Jeonghu Han; Kyu Hwan An; Hyoungsoo Kim; Joonhui Hur; Kiseok Yang; Kyutae Lim; Chang-Ho Lee; Joy Laskar

doi:10.1587/elex.11.20140523

This article has now been updated. Please use the final version.

Optimization of CMOS power-cell layout for improving junction breakdown

Ockgoo Lee, Jeonghu Han, Kyu Hwan An, Hyoungsoo Kim, Joonhui Hur, Kiseok Yang, Kyutae Lim, Chang-Ho Lee, Joy Laskar

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Keywords: CMOS, power cell, substrate resistance, junction breakdown, gate finger, gate finger width

JOURNAL FREE ACCESS Advance online publication

Article ID: 11.20140523

DOI https://doi.org/10.1587/elex.11.20140523

The final version of this article is now available: Vol. 11 (2014), No. 19 pp. 20140523-20140523

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Abstract

Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-µm CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.

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