Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation

Abstract

To improve the arithmetic performance of the conventional bit-stream squarer circuit based on sigma delta (ΣΔ) modulation, the method of bit translation is proposed. In addition, the original bit-stream squarer inside the bit-stream square root circuit is replaced with the proposed bit-stream squarer to reduce the arithmetic operation error. The performances of the proposed bit-stream squarer and square root circuit were verified through the simulation in Matlab. Compared with the conventional circuits, the proposed circuits can increase the calculation accuracy signally.