IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

This article has now been updated. Please use the final version.

Booth encoding modulo (2n-2p-1) multipliers
Lei LiSaiye LiPeng YangQingyu Zhang
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JOURNAL FREE ACCESS Advance online publication

Article ID: 11.20140588

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Abstract
In this express, we propose Booth encoding high-speed modulo (2n − 2p − 1) multipliers on the condition length of (Cout) ≤ min(2np, n + p), where Cout is the carry-out output of the carry save adder tree that is used to compress the partial products and the correction term after splitting, shifting and resetting. Synthesized results demonstrate that the proposed Booth encoding modulo (2n − 2p − 1) multipliers have a good delay performance.
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