抄録
We present design of an asynchronous digital pipeline based on stochastic resonance gates (SR gates). These gates allow mismatch-tolerant and low-power designs by utilizing the beneficial role of noise (stochastic resonance effect). However, unpredictable delays appear in SR gates due to their dependence on stochastic processes. Therefore, applications are found in asynchronous circuits. We demonstrate the performance of a three-stage-asynchronous pipeline with dual-rail data encoding. Electrical simulations were done for a 0.18-μm CMOS technology, and confirmed the pipeline performance regardless of transistor mismatches and consuming low power (100 picowatts). Moreover, experimental results based on a macrosystem confirmed the pipeline performance.
