抄録
This paper presents a low-power half-rate clock-embedded transceiver architecture that employs quarter-rate multiplexing/ de-multiplexing circuit technique, low-Vdd current-mode driver topology embedding half-rate clock, and multi-functional injection-locked oscillator (ILRO) for a digital clock and data recovery (CDR) design. The whole transceiver circuit was simulated in 65nm CMOS process and its feasibility was proved successfully operating at 10Gb/s across a band-limited channel. The achievable power efficiencies of the receiver and transceiver were 0.7mW/Gb/s and 1.1mW/Gb/s respectively.
