抄録
A 3.8-MHz Wien-bridge oscillator is designed in low-cost 0.35 μm CMOS process. The amplifier gain control is done by MOS capacitors rather than by more nonlinear MOS resistors. A differential amplitude control loop controls two MOS capacitors in differential manner, which greatly reduces the feedback loop bandwidth without using any off-chip filters, hence almost completely eliminate the unwanted operating point disturbance of the oscillator core. The fabricated chip consumes 0.22 mA from 2V supply, and shows -41.1 dB of second harmonic component and -94.3 dBc/Hz phase noise at 100 kHz offset.
