抄録
Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation. In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance. A new write mechanism is proposed to reduce the charging/discharging activity on the respective bit lines. The cell is simulated in terms of power, delay and static noise margin (SNM). The simulated results show that write and read power of the proposed LPR cell are reduced up to 78% and 50% at 0.7V (in 65nm technology) respectively compared to the 6T cell. The proposed design achieves 2.4x higher read static noise margin (SNM) than the 6T cell.
