Phase Noise Suppression Techniques for High Frequency Synthesizers in 65nm CMOS

Abstract

This paper describes several phase noise suppression techniques for X-band (8-12GHz) frequency synthesizer design in 65nm CMOS technologies. A low noise voltage generator for varactor DC biasing is proposed to minimize its contribution to VCO phase noise, which minimizes the out-of-band phase noise. A crystal oscillator with low noise biasing is proposed to prevent bias and supply noise from deteriorating its output phase noise, which improves the in-band phase noise. A frequency synthesizer prototype was implemented in 65nm CMOS technology and generates 8.6-12.4GHz output frequencies, with a measured phase noise performance of -90 dBc/Hz and -110 dBc/Hz at 10-kHz (in-band) and 1-MHz (out-of-band) frequency offset, respectively. The prototype draws 33mA current from a 1.2V power supply and the core circuit area is 0.2mm². The performance comparison demonstrates the prototype achieves the best phase noise performance among all published frequency synthesizers in X-band or higher frequencies.