抄録
A non-binary digital calibration scheme is proposed for split-capacitor digital-to-analog converter (DAC) in successive approximation register (SAR) analog-to-digital converter (ADC). This calibration scheme improves linearity without additional analog circuits and relaxes the requirement of the comparator offset. Furthermore, it allows bigger settling error for each capacitor in MSB array in normal operation. It is utilized in the design of a 10b 50MS/s SAR ADC in 65nm CMOS technology with the calibration circuitry integrated. Measurement results show a peak SNDR of 56.2dB, while consuming 0.82mW from 1.2V supply. The FOM is 31.1fJ/conv.-step and the ADC occupies 0.057mm2 active area, which proves the proposed scheme compared with our previous work without calibration.
