抄録
A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800 mV in TSMC 65nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.
