Parallelizing SHA-1
Keywords:
Cryptography,
Field-Programmable Gate Array (FPGA),
Hardware Implementation,
Hash Functions,
Secure Hash Algorithm (SHA)
Article ID: 12.20150371
Details
Article ID: 12.20150371
In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.
