On-chip Jitter Tolerance Measurement Technique with Independent Jitter Frequency Modulation from VCO in CDR

Abstract

We present an on-chip measurement technique to characterize the jitter tolerance of a clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates a modulated-charge-pump and a pulse generation circuits to apply a periodic triangular form voltage directly to the control voltage of CDR circuit. This jitter frequency generation scheme independent from the VCO in the CDR allows a wide and linear control of jitter. The modulated jitter amplitude range was 0.05 - 2UIpp at 10MHz, and the jitter frequency range was 100 KHz - 20MHz. The circuit was fabricated in 65nm CMOS, and the jitter tolerance was successfully measured at 5Gbps with a 2⁷-1 PRBS pattern. The accuracy was within 10% error from the external BER equipment measurement result. The whole CDR circuit consumes 29.9mW at a supply voltage of 1.2V.