抄録
As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominative RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0s or not at a time. A March-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.
