Charge sharing based 10T SRAM for low-power
論文ID: 13.20151033
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論文ID: 13.20151033
We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full VDD, and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45nm node show that the proposed 10T design has 2×read static noise margin, 71% reduction in total read and 48% reduction in total write power.
