High-speed demonstration of low-power 1k-bit shift-register memories using LR-biasing SFQ circuits

Toshihiro Takahashi; Ryo Numaguchi; Yuki Yamanashi; Nobuyuki Yoshikawa

doi:10.1587/elex.13.20160074

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High-speed demonstration of low-power 1k-bit shift-register memories using LR-biasing SFQ circuits

Toshihiro Takahashi, Ryo Numaguchi, Yuki Yamanashi, Nobuyuki Yoshikawa

著者情報

キーワード: SFQ circuits, shift register, memory, superconducting integrated circuits

ジャーナルフリー早期公開

論文ID: 13.20160074

DOI https://doi.org/10.1587/elex.13.20160074

この記事には本公開記事があります。

The final version of this article is now available: Vol. 13 (2016), No. 6 pp. 20160074-20160074

詳細

抄録

We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

責任著者(Corresponding author)

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