An offset distribution modification technique of stochastic flash ADC

Tomohiro Asano; Yusaku Hirai; Sadahiro Tani; Shinya Yano; Ikkyun Jo; Toshimasa Matsuoka

doi:10.1587/elex.13.20160115

This article has now been updated. Please use the final version.

An offset distribution modification technique of stochastic flash ADC

Tomohiro Asano, Yusaku Hirai, Sadahiro Tani, Shinya Yano, Ikkyun Jo, Toshimasa Matsuoka

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Keywords: stochastic flash ADC, comparator, mismatch, CMOS, genetic algorithm

JOURNAL FREE ACCESS Advance online publication

Article ID: 13.20160115

DOI https://doi.org/10.1587/elex.13.20160115

The final version of this article is now available: Vol. 13 (2016), No. 6 pp. 20160115-20160115

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Abstract

A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

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