An efficient digital calibration technique for timing mismatch in time-interleaved ADCs

Abstract

An efficient digital calibration technique for timing mismatch in time-interleaved ADCs is presented. It depends on the phase detection between a reference clock and the sampling clock of each sub-ADC in TIADC system. A method of variable delay line is used to compensate the timing mismatch. The mismatch detection and compensation form a feedback loop and can achieve a real-time tracking and correcting. Simulation results showed that this technique can have the timing mismatch calibrated quickly and correctly within the entire Nyquist sampling frequency by the virtue of a smaller hardware, and can be applied to any number of TIADC.