Mitigate Erroneous Operations of 2T-2MTJ STT-MRAM based on Dynamic Voltage Threshold

抄録

2T-2MTJ STT-MRAM suffers from the intrinsic stochastic switching behaviors of MTJ, “source degeneration” and leakage current problem of its access transistors, which could cause erroneous operations including write error and hold error. To mitigate those erroneous operations, Dynamic Voltage Threshold based High Voltage Threshold NMOS (HVT-nDTMOS) is used as access transistors of 2T-2MTJ to increase writing current and reducing leakage current. Simulation results show that the optimized design reduces write error rate by about 13.3% and 0.062‰reduction in hold error rate for each memory cell on the same condition of cell area and operating scheduling, compared with traditional 2T-2MTJ structure.