Prototyping Design of a Flexible DSP Block with Pipeline Structure for FPGA

Abstract

Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).