Low-Delay Parallel Chien Search Architecture for RS Decoder

Abstract

Sharing common subexpressions (CSs) in the logic expressions can reduce the total gates in hardware implementations of parallel Chien search. In this paper, we prove that sharing CSs will increase the delays of the hardware implementation. Based on the proof, a shortest-path-keep common subexpression elimination (SPK-CSE) algorithm is proposed. By using SPK-CSE algorithm, the output delays can be kept unchanged after sharing CSs. The parallel Chien search implemented with the proposed SPK-CSE algorithm can achieve the minimal delay.