Low-Delay Parallel Chien Search Architecture for RS Decoder

ZHANG Xiaoqiang; WU Ning; ZHOU Fang; LI Jianhua; YASIR

doi:10.1587/elex.13.20160729

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Low-Delay Parallel Chien Search Architecture for RS Decoder

ZHANG Xiaoqiang, WU Ning, ZHOU Fang, LI Jianhua, YASIR

著者情報

キーワード: Chien search, common subexpression elimination, critical path delay

ジャーナルフリー早期公開

論文ID: 13.20160729

DOI https://doi.org/10.1587/elex.13.20160729

この記事には本公開記事があります。

The final version of this article is now available: Vol. 13 (2016), No. 19 pp. 20160729-20160729

詳細

抄録

Sharing common subexpressions (CSs) in the logic expressions can reduce the total gates in hardware implementations of parallel Chien search. In this paper, we prove that sharing CSs will increase the delays of the hardware implementation. Based on the proof, a shortest-path-keep common subexpression elimination (SPK-CSE) algorithm is proposed. By using SPK-CSE algorithm, the output delays can be kept unchanged after sharing CSs. The parallel Chien search implemented with the proposed SPK-CSE algorithm can achieve the minimal delay.

責任著者(Corresponding author)

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