A 3.2-to-4.6GHz fast-settling all-digital PLL with feed forward frequency presetting

Abstract

This paper presents a 3.2-to-4.6GHz fast-settling all digital fractional-N phase-locked loop (ADPLL) for multimode multiband receivers. Firstly, in this ADPLL, the wideband digitally controlled oscillator (DCO) is designed with a constant frequency step in the Coarse Mode to ensure constant loop bandwidth in the whole frequency range. Secondly, a feed-forward presetting path between frequency command word (FCW) and oscillator tuning word in the Coarse Mode (OTW^C) is utilized to accelerate the locking process for large frequency hopping steps. Thirdly, an adaptive locked and unlocked controller (ALUC) is used to allow frequency mode (Coarse/Medium/Fine Mode) to shift automatically. Implemented in a 65nm CMOS process, the ADPLL on-chip part consumes 16mW at 1V voltage supply. The phase noise at 3.982GHz is −121.8dBc/Hz@1MHz. The ADPLL with a final bandwidth of 65kHz exhibits 55μs transient settling time for a 1.232 GHz frequency hopping.