A 2.4-GHz All-Digital Phase-Locked Loop With a Pipeline-ΔΣ Time-to-Digital Converter

Abstract

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. The proposed pipeline-ΔΣ TDC is based on two-stage time quantization with pulse-train time amplifiers. It achieves an SNDR of 80dB and a high resolution up to 0.23ps. A MASH 1-1-1 ΔΣ modulator based on vernier lines is used to achieve third-order noise shaping. The proposed ADPLL has been implemented in a 0.13-μm CMOS technology. The measurement results show a 12-mW total power consumption. The in-band and out-band phase noise are -91dBc/Hz@10kHz and -128dBc/Hz@1MHz, respectively. The RMS jitter and peak-peak jitter are 2.9ps and 21.5ps, respectively.