SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

Abstract

This paper presents a self-gated error resilient cluster of sequential cells (SGERC) to sample the critical data in wide-voltage operation for EDAC system. SGERC introduces latch-based clock gating technique to error resilient circuits and proposes a customized clock gate which has the ability of timing error self-correction with only two additional transistors added for the first time. Further, it totally eliminates the timing error detection circuits required by each critical register before and utilizes the data-driven clock gating circuits to generate timing error information. Simulation results show that SGERC design achieves 58.3% energy efficiency improvement compared with the baseline design and 19.4% over the latest EDAC design.