A New Compact Hardware Architecture of S-Box for Block Ciphers AES and SM4

抄録

In this paper, a new compact implementation of S-Box based on composite field arithmetic (CFA) is proposed for block ciphers AES and SM4. Firstly, using CFA technology, the multiplicative inverse (MI) over GF(2⁸) is mapped into GF((2⁴)²) and the new architecture of S-Box is designed. Secondly, the MI over GF(2⁴) is optimized by Genetic algorithm (GA), and the multiplication over GF(2⁴) and the constant matrix multiplications are optimized by delay-aware common sub-expression elimination (DACSE) algorithm. Finally, compared with the direct implementation, the area reduction of MI over GF((2⁴)²) and the new S-Box are up to 49.29% and 43.80%, severally. In 180nm 1.8V COMS technology, compared to the synthesized results of AES S-Box and SM4 S-Box, the area and power consumption of the new S-Box are reduced by 24.76% and 38.54%, respectively.