IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Design of Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression
Sang Muk LeeJi Hoon JangJung Hwan OhJi Kwang KimSeung Eun Lee
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JOURNALS FREE ACCESS Advance online publication

Article ID: 14.20170399

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Abstract

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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