A novel SEU hardened SRAM bit-cell design
Article ID: 14.20170413
Details
Article ID: 14.20170413
An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.
