Huaguo Liang1) 2),
Xiangsheng Fang2) 3),
1) School of Electronic Science&Applied Physics, Hefei University of Technology
2) School of Computer and Information, Hefei University of Technology
3) Department of Information Project, Anhui Institute of Economic Management
4) Department of Creative Informatics, Kyushu Institute of Technology
3D IC, TSV, pre-bond, testing, time interval, digital code
The final version of this article with its full bibliographical information is available. To access the article, click here (Vol. 14 (2017), No. 18 pp. 20170590-20170590).
Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45nm CMOS technology. The results show the effectiveness in the detection of time interval 10ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.
Edited and published by : The Institute of Electronics, Information and Communication Engineers Produced and listed by : Komiyama Printing Co., LTD.