1) School of Electronic Science & Applied Physics, Hefei University of Technology
2) State Key Laboratory of ASIC & System, Fudan Uniersity
3) School of Electronics and Information Technology, Sun Yat-sen University
heterogeneous, parallel turbo decoder, multi-core, SDR
The final version of this article with its full bibliographical information is available. To access the article, click here (Vol. 14 (2017), No. 18 pp. 20170768-20170768).
It has always been a challenging task to implement a turbo decoder because it's typically the most compute-intensive and time-consuming part in a wireless communication system. This becomes especially obvious when realizing a turbo decoder through CPUs or GPUs. In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor platform. A modified sliding-window algorithm is proposed to fully exploit the parallelism of turbo decoder, and a SIMD hardware module is designed for the multi-core processor to accelerate the decoding process. Synthesized result in a 65-nm CMOS process shows that the whole system can run at a maximum clock frequency of 830MHz, and a decoding throughput of 135 Mbps is achieved for a codeword block length of 6144 at 6 iterations. In addition, the speed-up rate compared to an unaccelerated implementation through the same multi-core platform is in the order of 800%.
Edited and published by : The Institute of Electronics, Information and Communication Engineers Produced and listed by : Komiyama Printing Co., LTD.