1) School of Electrical and Computer Engineering, UNIST
2) School of Computer and Information Engineering, Kwangwoon University
Voltage noise, IR drop, 3D IC, TSV, power delivery network (PDN), PEEC, multi-paired
The final version of this article with its full bibliographical information is available. To access the article, click here (Vol. 14 (2017), No. 18 pp. 20170792-20170792).
Three-dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise, and cause additional IR-drop in the power delivery network (PDN). In this work, we investigate and analyze the voltage noise in a multi-layer 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then, we propose a wire-added multi-paired on-chip PDN structure to reduce voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately a maximum 29% IR-drop reduction compared with the conventional PDN. In addition, we analyze the layer dependency on 3D IC between the conventional and the proposed PDN models.
Edited and published by : The Institute of Electronics, Information and Communication Engineers Produced and listed by : Komiyama Printing Co., LTD.