A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process

Xiaoyun Li; Houpeng Chen; Yu Lei; Qian Wang; Xi Li; Jie Miao; Zhitang Song

doi:10.1587/elex.14.20170899

This article has now been updated. Please use the final version.

A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process

Xiaoyun Li, Houpeng Chen, Yu Lei, Qian Wang, Xi Li, Jie Miao, Zhitang Song

Author information

Xiaoyun Li
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Houpeng Chen
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Yu Lei
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Qian Wang
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Xi Li
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Jie Miao
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences
Zhitang Song
State Key Laboratory of Functional Materials for Informatics; Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, University of Chinese Academy of Sciences

Keywords: Electrostatic discharge (ESD), mixed-voltage I/O, high trigger current, detection circuit, 28nm HKMG CMOS process

JOURNAL FREE ACCESS Advance online publication

Article ID: 14.20170899

DOI https://doi.org/10.1587/elex.14.20170899

The final version of this article is now available: Vol. 14 (2017), No. 21 pp. 20170899-20170899

Details

Abstract

A novel high performance 3×VDD-tolerant electrostatic discharging (ESD) detection circuit using only 1×VDD devices was presented in a 28nm 1.8V high-k metal-gate (HKMG) CMOS technology. A sub-path and an enhanced path were adopted in this novel design to increase its trigger current. Two small-sized PMOS transistors were employed to protect this circuit out of gate-oxide reliability issues under normal operating conditions. And there is only one capacitor in our novel circuit to maintain a small layout area. Under the ESD stress events, spectre-simulation results show that the trigger current of our proposed circuit can reach 36.4mA. And its leakage current is only 2.8nA at 27°C, 243nA at 120°C under normal operating conditions.

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