IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

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A Low Complexity LDPC-BCH Concatenated Decoder for NAND Flash Memory
Zhongjie ChenJin ShaChuan ZhangFeng Yan
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論文ID: 15.20180103

この記事には本公開記事があります。
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Low-density parity-check (LDPC) codes are widely used in NAND flash memory as an advanced error correction method due to their excellent correcting capability. The major challenge is the error floor problem. Dispersed array LDPC (DA-LDPC) code is highly structured and provides implementation convenience due to its regularity. In this paper, it is shown that the constructed (18289, 16384) DA-LDPC code suffers the error floor at BER of 10−9, which is far from the demand of flash memory error control. Carefully observing the error patterns in the error floor region, we propose a concatenation of BCH code to alleviate this issue. The error floor has been successfully brought down to BER of 10−14 by concatenating a BCH code with correcting capability of 14 bits. Compared to the standalone LDPC decoder, the concatenated decoder only consumes 7% extra hardware and the code rate penalty is less than 1%. Meanwhile, hardware implementation has shown that the throughput can achieve 3.52 Gbps with 6 iterations under a clock frequency of 200 MHz.

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© 2018 by The Institute of Electronics, Information and Communication Engineers
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