An Efficient Controlled LFSR Hybrid BIST Scheme

Abstract

A new hybrid built-in self-test (BIST) test scheme is proposed. The test scheme consists of two components: the free LFSR mode (pseudo-random test) and the controlled LFSR mode (deterministic test). In order to improve the test quality of pseudo-random test sequence, a forward-backward pseudo-random test generation method is proposed. As every shifted-in bit is fully used to generate the most efficient test and the ratio of do not care bits is maximized in the remaining test pattern repository, the proposed controlled LFSR test generation method can find the targeted pattern with the minimal number of shift, efficiently embedding the deterministic test set into test-per-clock stream. Simulation results demonstrate that the proposed method considering for layout constraints shows great advantages in test data storage and test application time compared with previous methods.