Article ID: 15.20180293
In this paper, a noise rejection circuit for level-shift gate drive ICs is proposed. This circuit is composed of a detection module and a pull down module with good process matching robustness and low circuit complexity. The dv/dt noise is removed by monitoring the interval of the IGBT gate-emitter voltage variation and locking the output logic in the period of the dv/dt noise comes. Spectre simulation has been performed with a 700V 0.6um BCD process model to verify the performance of the proposed noise rejection circuit which shows a full removal of 80 V/ns dv/dt noise and only 15ns increasing in propagation delay time.
