An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

Jeong Cho; Young-Jae Min

doi:10.1587/elex.15.20180331

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An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

著者情報

キーワード: Duty-cycle correction, Phase-skew correction, Successive approximation register (SAR), Quadrature data rate (QDR), DRAM

ジャーナルフリー早期公開

論文ID: 15.20180331

DOI https://doi.org/10.1587/elex.15.20180331

この記事には本公開記事があります。

The final version of this article is now available: Vol. 15 (2018), No. 9 pp. 20180331-20180331

詳細

抄録

A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented. To improve the correction time, this work adopts a successive approximation register controller for both duty-cycle and phase-skew correction. The proposed correction circuit has been fabricated in a 65nm CMOS technology with a die area of 0.086mm². The duty-cycle and phase-skew of 4-phase outputs are corrected with 56 cycles. The measured duty-cycle error and phase-skew are below ±1% and ±5ps, respectively.

責任著者(Corresponding author)

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