A low power and glitch-free circular rotation phase modulator for outphasing transmitter

抄録

This paper proposes an energy-efficient and glitch-free digital phase modulator for outphasing transmitter. The proposed modulator uses a path-shared tapped delay line (TDL) and a dynamical pseudo clock-gating control technique. These approaches lead a 64% lower power consumption compared conventional digital control delay lines (DCDLs). Moreover, the proposed modulator achieves circular rotational phase modulation, resulting a system EVM of -36.93 dB and ACLR of -50.96 dBc without extra shaping circuits or analog filters. The prototype modulator was fabricated in 130 nm CMOS process with an active area of 0.134 mm². Operating under 40 MHz frequency with 1.2V power supply, the proposed modulator consumes total power of 450 µW. In addition, this chip achieves an 80 ps coarse resolution with 4.7 ps RMS error and a minimum phase resolution of 0.96 ps.