A high-throughput network on-chip in full-mesh architecture

抄録

Just as Moores law dictates, technology scaling still continues in recent years. Thus increasing the number of on-chip cores continues to be the facto strategy to scale performance while interconnection networks remain important in multi-core chip systems. In this paper, we present a brand-new network-on-chip (NoC) based on full-mesh architecture - Full-Mesh NoC (FMN) that can provide high connectivity with low-radix routers. We give an example of implementation for a 64-node FMN system in 28 nm process. Results show that this FMN can achieve high frequency of 700 MHz while area requirement of each router is less than 0.035 mm². At last, we simulate a no-buffered FMN and a buffered FMN under uniform random traffic. Results show that the throughput of the no-buffered FMN can achieve the level of high-radix crossbar. The buffered FMN can achieve 2X throughput compared with the traditional buffered 2D-mesh NoC.