論文ID: 15.20180802
System-on-Chip (SoC) design using hardware Intellectual Property (IP) cores has become an integral part and pervasive practice in industries to realize error-free complex devices. However, IP vendors face major challenges in protecting hardware IPs against hardware Trojans and preventing revenue loss due to IP piracy. Obfuscation is an exact solution for protecting hardware IP against various attacks such as piracy, overbuilding and tampering. Logic locking technique allows locking outputs by fixed logic values and generates invalid output of the function if a wrong unlocking key was applied. In this paper, a novel technique called configurable Gate Diffusion Input (GDI) based logic obfuscation is proposed to enhance the security of hardware IPs. Configurable GDI based obfuscated cell inserts extra gates in the logic path of the circuit with minimum overheads to secure an IC from piracy and overbuilding. The proposed technique is simulated and synthesized using Synopsys software tool. Simulation results on ISCAS–89 benchmark circuits show that high levels of security are achieved through a well formulated obfuscation scheme at less than 10% area, power and delay overheads.
