An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO

Zixuan Wang; Hao Ding; Hao Xu; Cong Zhang; Shanwen Hu; Xincun Ji; Xiaojuan Xia; Zhikuang Cai

doi:10.1587/elex.15.20180889

この記事には本公開記事があります。本公開記事を参照してください。
引用する場合も本公開記事を引用してください。

An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO

Zixuan Wang, Hao Ding, Hao Xu, Cong Zhang, Shanwen Hu, Xincun Ji, Xiaojuan Xia, Zhikuang Cai

著者情報

Zixuan Wang
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Hao Ding
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Hao Xu
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Cong Zhang
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Shanwen Hu
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Xincun Ji
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Xiaojuan Xia
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
Zhikuang Cai
College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications

キーワード: All digitally phase-locked loop, time-to-digital converter, programmable-gain time amplifier, current-reuse

ジャーナルフリー早期公開

論文ID: 15.20180889

DOI https://doi.org/10.1587/elex.15.20180889

この記事には本公開記事があります。

The final version of this article is now available: Vol. 15 (2018), No. 22 pp. 20180889-20180889

詳細

抄録

An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper. The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA. The low-voltage DCO uses current-reuse structure to achieve lower and use bridging-capacitance technique to achieve high frequency resolution. The proposed design is validated by the ADPLL fabricated in the 65-nm CMOS technology. The measurement results show that the in-band and out-band phase noises are -90dBc/Hz@10kHz offset and -130dBc/Hz @1MHz offset, respectively. The RMS and peak-peak jitter are 1.24ps and 8.65ps respectively.

責任著者(Corresponding author)

J-STAGEへの登録はこちら（無料）