A SA-based Parallel Method for FPGA Placement
論文ID: 15.20180943
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論文ID: 15.20180943
In this paper, we present a serially-equivalent parallel method to accelerate FPGA placement. Our method is based on Simulated Annealing(SA) Algorithm: moves of placement blocks are processed concurrently on multiple threads. Two strategies are adopted here to guarantee serial equivalency: task switch of the master thread is used to handle data conflicts aroused by parallel; an efficient SA-based parallel framework is designed to obtain orderly flow of data. Our method is tested by doing placement for Xilinx xc4vlx200 FPGA chip. In a quad-core processor, a speedup of 1.8x,2.7x,3.4x is achieved on 2,3,4 threads. Compared to serial placer, placement results of our parallel placer are deterministic and have no quality loss.
