論文ID: 15.20180987
This brief proposes a differential power analysis (DPA) countermeasure for reconfigurable crypto processors. This method is verified on Field Programmable Gate Array (FPGA). The FPGA runs at clock frequency of 10 MHz, and AES algorithm is mapped on the array. Our countermeasure is based on random delay insertion (RDI), meanwhile keep pipeline processing of data. Effective DPA resistance is achieved by generating delays which subject to approximate uniform distribution and rearranging the processing order of data. This method can improve the difficulty of DPA and keep high throughput. This method also adapt to any other hardware pipeline style cipher processor.
