A 10-GS/s 8-bit 4-way interl-eaved Folding ADC in 0.18μm SiGe-BiCMOS

Huasen Liu; Danyu Wu; Lei Zhou; Yinkun Huang; Jian Luan; Xuan Guo; Dong Wang; Xuqiang Zheng; Jin Wu; Xinyu Liu

doi:10.1587/elex.16.20181079

This article has now been updated. Please use the final version.

A 10-GS/s 8-bit 4-way interl-eaved Folding ADC in 0.18μm SiGe-BiCMOS

Huasen Liu, Danyu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu

Author information

Huasen Liu
Institute of Microelectronics of Chinese Academy of Sciences
University of Chinese Academy of Sciences
Danyu Wu
Institute of Microelectronics of Chinese Academy of Sciences
Lei Zhou
Institute of Microelectronics of Chinese Academy of Sciences
Yinkun Huang
Institute of Microelectronics of Chinese Academy of Sciences
Jian Luan
Institute of Microelectronics of Chinese Academy of Sciences
Xuan Guo
Institute of Microelectronics of Chinese Academy of Sciences
Dong Wang
Institute of Microelectronics of Chinese Academy of Sciences
University of Chinese Academy of Sciences
Xuqiang Zheng
Institute of Microelectronics of Chinese Academy of Sciences
Jin Wu
Institute of Microelectronics of Chinese Academy of Sciences
Xinyu Liu
Institute of Microelectronics of Chinese Academy of Sciences

Keywords: Analog-to-digital converter, analog input multiplexer, SiGe BiCMOS, time-interleaved, track-and-hold

JOURNAL FREE ACCESS Advance online publication

Article ID: 16.20181079

DOI https://doi.org/10.1587/elex.16.20181079

The final version of this article is now available: Vol. 16 (2019), No. 3 pp. 20181079-20181079

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Abstract

In this paper, a time-interleaved 10-GS/s 8-bit analog-to-digital converter (ADC) fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. A 4x4 input multiplexer with good isolation and wide input bandwidth is proposed, which enables the ADC to support 1/2/4-channel sampling modes. In the track-and-hold (THA) stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the overshoot effect of the SEF output. The ADC achieves spurious free dynamic range (SFDR) > 52dBc and effective number of bits (ENOB) > 6.8 in low input frequencies. The analog input bandwidth is 5.6GHz.

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