A 0.07-3GHz wideband front-end for SDR receiver with 2.3dB NF and 12dBm IIP₃ in 65nm CMOS

Abstract

This paper presents a wideband (0.07-3GHz) receiver front-end realized in 65nm CMOS technology for mobile Software-Defined Radio (SDR) applications. A more power-efficient wideband common-gate low-noise amplifier (LNA) featuring a common-source path for noise-canceling is proposed to trade-off linearity and noise figure (NF). A current commutating down conversion passive mixer with transimpedance amplifier is applied to achieve low flicker noise and high linearity with low supply voltage. Measurements show that the front-end achieves conversion gain higher than 42dB. The measured NF ranges from 2.28 to 3.68dB in the covered frequency range and IIP₃ varies from 9 to 12dBm versus different frequencies. The front-end occupies an active area of 0.8mm² and consumes a power of 40mW from 1.2V supply voltage.