Article ID: 16.20181118
The current paper presents an inverter chain with parallel output nodes design for the purpose of eliminating the single-event transient (SET) pulse. The structure of parallel output nodes combined with the layout utilizing isolation approach can eliminate the SET pulse substantially. As compared with the conventional inverter chain as well as the inverter chain of source-isolation approach and the duplicated inverter chains with C-element, the simulation results illustrate that the proposed inverter chain manifests an effective improvement of immunity to SET. With regard to P-hit, the proposed inverter chain is capable of attaining a stable output irrespective of the state of the struck PMOS being OFF or ON. With regard to N-hit, the proposed inverter chain can also maintain the final output steadily. As long as the SET pulse is not generated at the eventual output node, the pulse can be eliminated by the proposed inverter chain. Besides that, the proposed approach is also applicable to the circuits with the structure like inverter chain.